SH7065 Datasheet, PDF (177/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Oscillator
RES
HSTBY
Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Oscillation Reset exception
settling time handling
Figure 4.8 Hardware Standby Mode Timing
4.13 Module Standby Function
4.13.1 Transition to Module Standby Function
Setting an MSTP bit to 1 in module stop mode control register 1 or 2 (MSTPCR1, MSTPCR2)
enables the clock supply to the corresponding on-chip peripheral module to be halted. Use of this
function allows power consumption to be reduced in normal operation and in sleep mode.
The correspondence between the MSTP bits and on-chip peripheral modules is shown in table
4.16.
In the module standby state, the SCI and A/D registers are initialized. Other registers retain their
states prior to halting of the module.
Registers of modules set to the module standby state cannot be read or written to.
Rev. 5.00 Sep 11, 2006 page 155 of 916
REJ09B0332-0500