SH7065 Datasheet, PDF (537/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 13 Watchdog Timer
13.3.2 Operation in Interval Timer Mode
Figure 13.5 illustrates WDT operation in interval timer mode. To use the WDT as an interval
timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. When the WDT is operating as
an interval timer, an interval timer interrupt (ITI) is generated each time TCNT overflows. This
function can be used to generate interrupt requests at regular intervals.
TCNT value
H'FF
Overflow Overflow Overflow Overflow
H'00
Time
WT/IT = 0 ITI
ITI
ITI
ITI
TME = 1
Legend:
ITI: Interval timer interrupt request generation
Figure 13.5 Operation in Interval Timer Mode
13.3.3 Operation When Clearing Software Standby Mode
The WDT is used when software standby mode is cleared by an NMI interrupt. When software
standby mode is used, the WDT should be set as described in 1 below.
1. Settings before transition to software standby mode
Before making a transition to software standby mode, the WDT must be halted by clearing the
TME bit to 0 in the timer control/status register (TCSR). A transition to software standby mode
cannot be made while the TME bit is set to 1. Also set bits CKS2 to CKS0 in TCSR so that the
timer counter (TCNT) overflow period is at least as long as the oscillation settling time (see
section 22.3, AC Characteristics Test Conditions).
2. Operation when software standby mode is cleared
When an NMI interrupt is generated in software standby mode, the oscillator starts operating
and TCNT begins counting up on the clock selected with bits CKS2 to CKS0 prior to the
transition to software standby mode.
When TCNT overflows (from H'FF to H'00), the clock is judged to be stable and ready for use,
and clocks are supplied throughout the chip. This clears software standby mode.
Rev. 5.00 Sep 11, 2006 page 515 of 916
REJ09B0332-0500