SH7065 Datasheet, PDF (95/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.24 Branch Instructions
Instruction
Instruction Code
Operation
BF label
10001011dddddddd
When T = 0,
disp × 2 + PC → PC;
when T = 1, nop
BF/S label
10001111dddddddd
Delayed branch;
when T = 0,
disp × 2 + PC → PC;
when T = 1, nop
BT label
10001001dddddddd
When T = 1,
disp × 2 + PC → PC;
when T = 0, nop
BT/S label
10001101dddddddd
Delayed branch;
when T = 1,
disp × 2 + PC → PC;
when T = 0, nop
BRA label
1010dddddddddddd Delayed branch,
disp × 2 + PC → PC
BRAF Rm
0000mmmm00100011 Delayed branch,
Rm + PC → PC
BSR label
1011dddddddddddd
Delayed branch,
PC → PR,
disp × 2 + PC→ PC
BSRF Rm
0000mmmm00000011
Delayed branch,
PC→ PR,
Rm + PC→ PC
JMP @Rm
0100mmmm00101011 Delayed branch,
Rm→ PC
JSR @Rm
0100mmmm00001011 Delayed branch,
PC→ PR, Rm→ PC
RTS
0000000000001011 Delayed branch,
PR→ PC
Note: * One state when the branch is not executed.
Section 2 CPU
Execution
States T Bit
3/1^*
—
2/1^*
—
3/1^*
—
2/1^*
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
Rev. 5.00 Sep 11, 2006 page 73 of 916
REJ09B0332-0500