SH7065 Datasheet, PDF (561/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 2—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived
for at least 15 etu after the stop bit of the last data received.
Bit 2: DR
Description
0
Reception is in progress or has ended normally and there is no receive data
left in SCFRDR
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to DR after reading all remaining receive data and the
state of DR = 1*¹
1
No further receive data has arrived, and SCFRDR contains fewer than the
receive trigger set number of data bytes
[Setting condition]
When SCFRDR contains fewer than the receive trigger set number of receive
data bytes, and no further data has arrived for at least 15 etu after the stop bit
of the last data received^*2
Notes: 1. All remaining receive data should be read before clearing the DR flag.
2. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
etu: Elementary time unit = sec/bit
Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is
to be continued when a framing error or parity error occurs in receive data (ER = 1).
Bit 1: EI
Description
0
Receive operation is halted when framing error or parity error occurs during
reception (ER = 1)
(Initial value)
1
Receive operation is continued when framing error or parity error occurs during
reception (ER = 1)
Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI
= 1, receive data is sent to SCFRDR even if it contains an error.
Rev. 5.00 Sep 11, 2006 page 539 of 916
REJ09B0332-0500