SH7065 Datasheet, PDF (398/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the internal clock is counted using both edges, the input clock period is halved (e.g. Pφ/4
both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this
setting is ignored and the phase counting mode setting has priority.
Bit 4: CKEG1
Bit 3: CKEG0
Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is Pφ/4 or slower. This setting is
ignored if the input clock is Pφ/1, or when overflow/underflow of another channel is selected.
Bits 2, 1, and 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 10.4 shows the
clock sources that can be set for each channel.
Table 10.4 TPU Clock Sources
Internal Clock
Channel
Pφ/1
Pφ/4
Pφ/
16
Pφ/
64
Pφ/
256
0
OOO O
1
O
O
O
O
O
2
OOO O
3
O
O
O
O
O
4
OOO O
5
O
O
O
O
O
Legend:
O: Setting available
Blank: No setting
Pφ/
1024
Pφ/
4096
External Clock
Overflow/
Underflow
TCLKA TCLKB TCLKC TCLKD ^{on Another}
Channel
O
O
O
O
O
O
O
O
O
O
O
OO
O
O
O
O
O
O
O
O
Rev. 5.00 Sep 11, 2006 page 376 of 916
REJ09B0332-0500