SH7065 Datasheet, PDF (421/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bit 5: TCIEU
0
1
Section 10 16-Bit Timer Pulse Unit (TPU)
Description
Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
(Initial value)
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by
the TCFV flag in TSR when TCFV is set to 1.
Bit 4: TCIEV
0
1
Description
Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
(Initial value)
Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the
TGFD bit in TSR when TGFD is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3: TGIED
0
1
Description
Interrupt requests (TGID) by TGFD bit disabled
Interrupt requests (TGID) by TGFD bit enabled
(Initial value)
Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the
TGFC bit in TSR when TGFC is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2: TGIEC
0
1
Description
Interrupt requests (TGIC) by TGFC bit disabled
Interrupt requests (TGIC) by TGFC bit enabled
(Initial value)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit in TSR when TGFB is set to 1.
Bit 1: TGIEB
0
1
Description
Interrupt requests (TGIB) by TGFB bit disabled
Interrupt requests (TGIB) by TGFB bit enabled
(Initial value)
Rev. 5.00 Sep 11, 2006 page 399 of 916
REJ09B0332-0500