SH7065 Datasheet, PDF (825/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 22 Electrical Characteristics
Item
Bus start delay time 1
Bus start delay time 2
Symbol Min
tBSD1
2^*
tBSD2
2^*
Max
25
25
Byte strobe delay time 1
Byte strobe delay time 2
Output enable delay time 1
Output enable delay time 2
Column address hold time
(read)
Column address hold time
(write)
tXXBSD1
tXXBSD2
tOED1
tOED2
tCAH
tCAH
2^*
25
2^*
25
2^*
25
2^*
25
tcyc × (w + 1.5) − 15

tcyc × (TCAS + 0.5) − 15 
Unit Figure
ns
Figure 22.9,
ns
Figure 22.10,
Figure 22.12,
Figure 22.13,
Figure 22.14,
Figure 22.16,
Figure 22.19,
Figure 22.20
ns
Figure 22.9,
ns
Figure 22.10
ns
Figure 22.14,
ns
Figure 22.16
ns
Figure 22.12,
Figure 22.13,
ns
Figure 22.14,
Figure 22.15
Column address setup time tASC
(read)
tcyc × 0.5 − 17.5

ns
Column address setup time tASC
tcyc × (w + 0.5) − 17.5 
ns
(write)
Notes: TPC is the set value of the TPC bit in DCR1.
TCAS is the set value of the TCAS bit in DCR2.
W is the DWW set number in a write from the CPU, the DDWW set number in a DMAC
single address write, or the number of waits via the WAIT pin.
tcyc is the CKE cycle (min. 33.3 ns).
* The minimum (Min) values for delay times are reference values.
Rev. 5.00 Sep 11, 2006 page 803 of 916
REJ09B0332-0500