SH7065 Datasheet, PDF (299/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
CKE
Tr
Tce1
Tce2
Tce2
Tce2
Tce3
A25–A0
CSn
Row
Column
Column
Column
Column
RDWR
RASn
CASxxn
(OE)
D31–D0
(read)
D31–D0
(write)
BS
DACKn
Figure 8.23 DRAM Burst Access Basic Timing in EDO Mode
RAS Down Mode
Even if burst operation is selected, it may happen that DRAM accesses are not consecutive, but are
interrupted by an access to a different space. With the normal setting, the RAS signal is
temporarily negated while a different space is being accessed, and must be reasserted to restart
burst operation when DRAM is next accessed. This is known as RAS up mode. However, it is
possible to keep the RAS signal asserted while a different space is being accessed, enabling burst
operation to be continued when the same DRAM row address is next accessed. This is known as
RAS down mode.
Rev. 5.00 Sep 11, 2006 page 277 of 916
REJ09B0332-0500