M16C65 Datasheet, PDF (815/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
31. Precautions
31.23 Notes on Multi-Master I²C-bus Interface
31.23.1 Limitation on CPU Clock
When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers
listed in Table 25.4 “Register Configuration”. Set the CM07 bit to 0 (main clock, PLL clock, or on-chip
oscillator clock) to access these registers.
31.23.2 Register Access
Notes are described to access the I2C interface control registers. The period from the rising edge of 1st
clock of slave address or one-byte data transmission/reception to the falling edge of an ACK clock is
considered as “period of transmission/reception”. When the ACKCLK bit is 0 (no ACK clock), the period
of transmission/reception is from the rising edge of 1st clock of slave address or one-byte data
transmission/reception to the falling edge of 8th clock.
31.23.2.1 S00 Register
Do not write to the S00 register during transmission/reception.
31.23.2.2 S10 Register
Do not change bits other than the IHR bit in the S10 register during transmission/reception.
31.23.2.3 S20 Register
Do not change bits other than the ACKBIT bit in the S20 register during transmission/reception.
31.23.2.4 S3D0 Register
• Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register.
• Bits ICK1 and ICK0 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface dis-
abled).
31.23.2.5 S4D0 Register
Bits ICK4 to ICK2 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface dis-
abled).
31.23.2.6 S10 Register
• Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register.
• Do not write to the S10 register when bits MST and TRX change their values.
Figure 25.13 “Start Condition Detection” to Figure 25.15 “Operation After Completion of Slave Address/
Data Transmit/Receive” shows when bits MST and TRX change.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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