M16C65 Datasheet, PDF (550/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.1.5 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) is 1 (reverse), the data written to the UiTB
register has its logic reversed before being transmitted. Similarly, the received data has its logic
reversed when read from the UiRB register. Figure 23.9 shows Serial Data Logic.
(1) UiLCH bit in the UiC1 register = 0 (no reverse)
Transmit/receive clock ^H
L
TXDi ^H
(no reverse) L
D0 D1 D2 D3 D4 D5 D6 D7
(2) UiLCH bit in the UiC1 register = 1 (reverse)
Transmit/receive clock ^H
L
TXDi ^H
(reverse) L
D0 D1 D2 D3 D4 D5 D6 D7
The above applies under the following conditions.
- The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge of the transmit/receive clock).
- The UFORM bit in the UiC0 register is 0 (LSB first).
i = 0 to 2, 5 to 7
Figure 23.9 Serial Data Logic
23.3.1.6 Transmit/Receive Clock Output from Multiple Pins (UART1)
Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transmit/receive clock
output pins (see Figure 23.10). This function can be used when the selected transmit/receive clock
for UART1 is an internal clock.
MCU
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
IN
IN
CLK
CLK
Transmit/receive enabled when the
Transmit/receive enabled when the
CLKMD0 bit in the UCON register is 0 CLKMD0 bit in the UCON register is 1
The above applies under the following conditions.
- The CKDIR bit in the U1MR register is 0 (internal clock).
- The CLKMD1 bit in the UCON register is 1 (transmit/receive clock output from multiple pins).
Figure 23.10 Transmit/Receive Clock Output from Multiple Pins
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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