M16C65 Datasheet, PDF (170/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
9. Power Control
Table 9.3 Clock Related Bit Setting and Modes
Mode
CM2 Register CM1 Register CM0 Register FRA0 Register
CM21
CM14 CM11 CM07 CM05 CM04 FRA01 FRA00
High-speed mode,
medium-speed mode
0
-
0
0
0
-
-
-
PLL operating mode
0
-
1
0
0
-
-
-
40 MHz on-chip oscillator mode
1
-
0
0
-
-
1
1
125 kHz on-chip oscillator mode
1
0
0
0 0 ⁽¹⁾ -
0
1 ⁽¹⁾
125 kHz on-chip oscillator low
power mode
1
0
0
0
1
-
0
0
Low-speed mode
-
-
0
1 0 ⁽¹⁾ 1
-
1 ⁽¹⁾
Low power mode
-
-
0
1
1
1
-
0
Note:
1. Both or either the main clock and fOCO-F are oscillated
Table 9.4 Selecting Clock Division Related Bits ⁽¹⁾
Division
CM1 Register
Bits CM17 to CM16
CM0 Register
CM16 bit
Divide-by-1 (no division) ⁽²⁾
00b
0
Divide-by-2
01b
0
Divide-by-4
10b
0
Divide-by-8
-
1
Divide-by-16
11b
0
Notes:
1.
2.
While in high-speed mode, medium-speed mode, PLL operating mode, 125 kHz on-chip oscillator
mode, or 125 kHz on-chip oscillator low power mode.
Select divide-by-1 (no division) in high-speed mode.
Table 9.5 Example Settings for 40 MHz On-Chip Oscillator Mode Division Related Bits
Division
CPU Clock Frequency
CM1 Register
Bits CM17 to CM16
CM0 Register
CM06 bit
Divide-by-2
Approx. 20 MHz
00b (divide-by-1 (no division)) 0
Divide-by-4
Approx. 10 MHz
01b (divide-by-2)
0
Divide-by-8
Approx. 5 MHz
10b (divide-by-4)
0
Divide-by-16
Approx. 2.5 MHz
-
1 (divide-by-8)
Divide-by-32
Approx. 1.25 MHz
11b (divide-by-16)
0
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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