M16C65 Datasheet, PDF (552/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and bit order.
Table 23.9 lists the UART Mode Specifications.
Table 23.9 UART Mode Specifications
Item
Data format
Transmit/receive
clock
Specification
• Character bits
• Start bit
• Parity bit
• Stop bit
: Selectable from 7, 8, or 9 bits
: 1 bit
: Selectable from odd, even, or none
: Selectable from 1 bit or 2 bits
• The CKDIR bit in the UiMR register = 0 (internal clock):
-₁---₆----₍--_n-^f--^j--₊-----₁----_{) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh}
• CKDIR bit = 1 (external clock):
-₁---₆--^f--₍^E--_n--^X---₊--^T---₁----_{) fEXT: Input from CLKi pin n: Setting value of UiBRG register 00h to FFh}
Transmission and Selectable from CTS function, RTS function or CTS/RTS function disabled
reception control
Transmission
start conditions
To start transmission, satisfy the following requirements.
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
• If CTS function is selected, input on the CTSi pin is low.
Reception start
conditions
To start reception, satisfy the following requirements.
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
Interrupt request Transmit interrupt: One of the following can be selected.
generation timing _{• The UiIRS bit = 0 (transmit buffer empty): When transferring data from the UiTB register to the UARTi}
transmit register (at start of transmission)
• The UiIRS bit =1 (transmission completed): When the serial interface completes sending data from the
UARTi transmit register
Receive interrupt:
• When transferring data from the UARTi receive register to the UiRB register (at completion of
reception)
Error detection _{• Overrun error} (1)
This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB
register and receives the bit one before the last stop bit of the next unit of data.
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when the number of 1s of the parity bit and character bit does not match the set
value of the PRY bit in the UiMR register.
• Error sum flag
This flag is set to 1 when an overrun, framing, or parity error occurs.
Selectable
functions
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O
data are reversed.
• Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins.
i = 0 to 2, 5 to 7
Note:
1. If an overrun error occurs, the receive data of the UiRB register will be undefined. The IR bit in the SiRIC register
remains unchanged.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 517 of 791