M16C65 Datasheet, PDF (107/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
6. Resets
6.4.8 Watchdog Timer Reset
The MCU resets the pins, CPU, and SFRs when the PM12 bit in the PM1 register is 1 (reset when
watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program
at the address determined by the reset vector. The fOCO-S divided by 8 is automatically selected as
the CPU clock after reset.
The WDR bit in the RSTFR register becomes 1 (watchdog timer reset detected). Some SFRs are not
reset at watchdog timer reset. Refer to 4. “Special Function Registers (SFRs)” for details. The
processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.
The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal
RAM, the internal RAM is in an undefined state.
Refer to 15. “Watchdog Timer” for details.
6.4.9 Software Reset
The MCU resets the pins, CPU, and SFRs when the PM03 bit in the PM0 register is 1 (MCU reset).
Then the MCU executes the program at the address determined by the reset vector. The fOCO-S
divided by 8 is automatically selected as the CPU clock after reset.
The SWR bit in the RSTFR register becomes 1 (software reset detected). Some SFRs are not reset at
software reset. Refer to 4. “Special Function Registers (SFRs)” for details. The processor mode
remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.
The internal RAM is not reset.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 72 of 791