M16C65 Datasheet, PDF (556/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Example of Receive Timing When Character Bit Length is 8 Bits
(Parity Disabled, One Stop Bit)
UiBRG count
source
RE bit in
1
UiC1 register 0
RXDi
Start bit
Stop bit
D0
D1
D7
Sampled as low
Receive data taken in
Transmit/
receive clock
RI bit in
Reception triggered when transmit/receive Transferred from UARTi receive register
1 _{clock is generated by falling edge of start bit. to UiRB register.}
UiC1 register 0
High
RTSi
Low
IR bit in
1
SiRIC register 0
Set to 0 by an interrupt request acknowledgement or by a program.
The above timing diagram applies when the register bits are set as follows:
· The PRYE bit in the UiMR register = 0 (parity disabled)
· The STPS bit in the UiMR register = 0 (1 stop bit)
· The CRD bit in the UiC0 register = 0 (CTSi/RTSi enabled)
· The CRS bit in the UiC0 register = 1 (RTSi selected)
i = 0 to 2, 5 to 7
Figure 23.13 Receive Timing in UART Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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