M16C65 Datasheet, PDF (72/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
3. Address Space
3.3 Accessible Area in Each Mode
The accessible area varies depending on processor mode and control bit status. Figure 3.3 shows
Accessible Area in Each Mode.
In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.
In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.
Address space is expandable to 4 Mbytes with the memory capacity-enhancing feature.
In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is
expandable to 4 Mbytes with the memory capacity-enhancing feature. Assign ROM to the fixed vector
table addresses from FFFDCh to FFFFFh.
00000h
00400h
0D000h
0D800h
0E000h
10000h
14000h
Single-Chip Mode
SFR
Internal RAM
Reserved area
SFR
Reserved area
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
Reserved area
Memory Expansion Mode
00000h
00400h
SFR
Internal RAM
0D000h
0D800h
0E000h
10000h
14000h
27000h
28000h
Reserved area
SFR
External area
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
External area
Reserved area
External area
40000h
Reserved area
Microprocessor Mode
00000h
00400h
SFR
Internal RAM
0D000h
0D800h
Reserved area
SFR
External area
27000h
28000h
Reserved area
External area
Internal ROM
(program ROM 1)
Internal ROM
(program ROM 1)
FFFFFh
FFFFFh
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
Single-chip mode and memory expansion mode
- The PM10 bit in the PM1 register is set to 1
(addresses from 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is set to 1
(the entire internal RAM and entire program ROM 1 from address 80000h are usable)
- The IRON bit in the PRG2C register is set to 1
(program ROM 1 addresses from 40000h to 7FFFFh enabled)
Microprocessor mode
- The PM10 bit is set to 0 (addresses from 0E000h to 0FFFFh are used as CS2 area)
- The PRG2C0 bit is set to 1 (program ROM 2 disabled)
Figure 3.3 Accessible Area in Each Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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