English
Language : 

M16C65 Datasheet, PDF (269/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60
Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.5 Hardware Interrupts
Hardware interrupts are classified into two types: special interrupts and peripheral function interrupts.
14.5.1 Special Interrupts
Special interrupts are non-maskable interrupts.
14.5.1.1 NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
about the NMI interrupt, refer to 14.9 “NMI Interrupt”.
14.5.1.2 DBC Interrupt
Do not use this interrupt because it is provided exclusively for use by development tools.
14.5.1.3 Watchdog Timer Interrupt
The interrupt is generated by the watchdog timer. Once a watchdog timer interrupt is generated, be
sure to refresh the watchdog timer. For details about the watchdog timer, refer to 15. “Watchdog
Timer”.
14.5.1.4 Oscillation Stop and Re-Oscillation Detection Interrupt
The interrupt is generated by the oscillation stop and re-oscillation detection function. For details
about the oscillation stop and re-oscillation detection function, refer to 8. “Clock Generator”.
14.5.1.5 Voltage Monitor 1, Voltage Monitor 2
The interrupt is generated by the voltage detection circuit. For details about the voltage detection
circuit, refer to 7. “Voltage Detector”.
14.5.1.6 Single-Step Interrupt
Do not use this interrupt because it is provided exclusively for use by development tools.
14.5.1.7 Address Match Interrupt
When the AIER0 or AIER1 bit in the AIER register, or the AIER20 or AIER21 bit in the AIER2 register
is 1 (address match interrupt enabled), an address match interrupt is generated immediately before
executing an instruction at the address indicated by the corresponding registers RMAD0 to RMAD3.
For details about the address match interrupt, refer to 14.11 “Address Match Interrupt”.
14.5.2 Peripheral Function Interrupts
A peripheral function interrupt occurs when a request from a peripheral function in the MCU is
acknowledged. Peripheral function interrupts are maskable interrupts. See Table 14.6 and Table 14.7
“Relocatable Vector Tables”. Refer to the descriptions of each function for details on how the
corresponding peripheral function interrupt is generated.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 234 of 791