M16C65 Datasheet, PDF (66/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
1. Overview
Table 1.22 Pin Functions (80-Pin Package) (2/2)
Signal Name
Serial interface
UART0 to UART2,
UART5
Pin Name
CTS0, CTS1,
CTS5
RTS0, RTS1,
RTS5
I/O
Power
Supply
Description
I VCC1
Input pins to control data transmission
O VCC1
Output pins to control data reception
CLK0, CLK1,
CLK5
I/O VCC1
Transmit/receive clock I/O pins
RXD0 to RXD2,
RXD5
I VCC1
Serial data input pins
TXD0 to TXD2,
TXD5
O VCC1
Serial data output pins ⁽¹⁾
CLKS1
O VCC1
Output pin for transmit/receive clock multiple-pin
output function
UART0 to UART2,
UART5
I²C mode
SDA0 to SDA2,
SDA5
SCL0 to SCL2,
SCL5
I/O VCC1
I/O VCC1
I²C mode serial data I/O pins
I²C mode transmit/receive clock I/O pins
Serial
interface
SI/03, SI/04
CLKS3, CLKS4
SIN4
SOUT3, SOUT4
I/O VCC1
I VCC1
O VCC1
Transmit/receive clock I/O pins
Serial data input pins
Serial data output pins
Multi-master I²C-bus ^SDAMM
Interface
SCLMM
I/O VCC1
I/O VCC1
Serial data I/O pin (output is N-channel open drain)
Transmit/receive clock I/O pin (output is N-channel
open drain)
CEC I/O
CEC
I/O VCC1
CEC I/O pin (output is N-channel open drain)
Reference
voltage input
VREF
I VCC1
Reference voltage input pins for the A/D converter
and D/A converter
A/D
converter
AN0 to AN7
AN0_0 to AN0_7
AN2_0 to AN2_7
ADTRG
I VCC1
I VCC1
I VCC1
Analog input pins for the A/D converter
Input pin for an external A/D trigger
ANEX0, ANEX1
I VCC1
Extended analog input pin for the A/D converter
D/A
converter
DA0, DA1
O VCC1
Output pin for the D/A converter
I/O port
P0_0 to P0_7
P2_0 to P2_7
P3_0 to P3_7
P5_0 to P5_7
P6_0 to P6_7
P8_0 to P8_7
P10_0 to P10_7
I/O VCC1
8-bit CMOS I/O ports. A direction register determines
whether each pin is used as an input port or an output
port. A pull-up resistor may be enabled or disabled for
input ports in 4-bit units.
P8_5 is an N-channel open drain output port. No pull-
up resistor is provided. P8_5 is an input port for
verifying the NMI pin level and shares a pin with NMI.
P4_0 to P4_3
P7_0, P7_1
P7_6, P7_7
P9_0,
P9_2 to P9_7
I/O VCC1
I/O ports having equivalent functions to P0.
However, P7_0 and P7_1 are N-channel open drain
output ports. No pull-up resistor is provided.
Note:
1. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins by a program.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 31 of 791