M16C65 Datasheet, PDF (321/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
fC32
fOCO-S
fOCO-F
f64TIMAB
f32TIMAB
f8TIMAB
f1TIMAB
or f2TIMAB
Data Bus
PWMFSi
TAi1 register
Count source select
TAi register
TCK1 to TCK0 ^TCS3
00
or
01
TCS7
0
10
11
TCS2 to TCS0
1
or TCS6 to TCS4
000
·Timer:
TMOD1 to TMOD0 = 00, MR2 = 0
·One-shot timer:
TMOD1 to TMOD0 = 10
·Pulse width modulation,
TMOD1 to TMOD0,
programmable output: TMOD1 to TMOD0 = 11 MR2
·Timer (gate function):
TMOD1 to TMOD0 = 00, MR2 = 1
·Event counter: TMOD1 to TMOD0 = 01
Reload register
001
010
011
100
101
110
Polarity
select
TAiIN
00
01
TB2 overflow ⁽¹⁾ ₁₀
TAj overflow ⁽¹⁾
TAk overflow ⁽¹⁾
11
TAiS
Decrement
TAiUD
To external
trigger circuit
Counter
Increment/decrement
Always decrement except
in event counter mode
00
10
11
01
TMOD1 to TMOD0
TAiTGH to TAiTGL
TAiOUT
POFSi
0
MR0
Toggle flip-flop
1
Note:
i = 0 to 4
j = i - 1, except j = 4 if i = 0
k = i + 1, except k = 0 if i = 4
1. Overflow or underflow
TAi
TAj
TAk
TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR0 : Bits in the TAiMR register
TAiTGH to TAiTGL : Bits in the ONSF register when i=0, bits in the TRGSR register when i = 1 to 4
TAiS
: Bits in the TABSR register
TAiUD
: Bits in the UDF register
TCS0 to TCS7 : Bits in the registers TACS0 to TACS2
POFSi
: Bits in the TAPOFS register
PWMFSi
: Bits in the PWMFS register
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
Figure 17.3 Timer A Block Diagram
Table 17.3 I/O Ports
Pin Name
I/O Type
Function
TAiIN
Input ⁽¹⁾
Gate input (timer mode)
Count source input (event counter mode)
Two-phase signal input (event counter mode (two-phase pulse
signal processing))
Trigger input (one-shot timer mode, PWM mode)
TAiOUT
Output ⁽²⁾
Pulse output (timer mode, event counter mode, one-shot timer
mode, PWM mode, and programmable output mode)
Input ⁽¹⁾
Increment/decrement select input (event counter mode)
Two-phase pulse input (event counter mode (two-phase pulse
signal processing))
ZP
Input ⁽¹⁾
Z-phase (counter initialization) input (event counter mode (two-
phase pulse signal processing))
i = 0 to 4; however, i = 2, 3, 4 for two-phase pulse input, and i = 1, 2, 4 in programmable output mode
Notes:
1. When using pins TAiIN, TAiOUT, and ZP for input, set the port direction bits corresponding to the
pins to 0 (input mode).
2. The TA0OUT pin is an N-channel open-drain output.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 286 of 791