M16C65 Datasheet, PDF (569/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Table 23.19 STSPSEL Bit Functions
Function
Output of pins SCLi
and SDAi
Start/stop condition
interrupt request
generation timing
STSPSEL = 0
Output of transmit/receive clock and data
Output of start/stop condition is
accomplished by a program using ports
(not automatically generated in
hardware).
Detection of start/stop condition
STSPSEL = 1
Output of a start/stop condition
according to bits STAREQ, RSTAREQ,
and STPREQ
Completion of start/stop condition
generation
(1) Slave mode
CKDIR = 1 (external clock)
STSPSEL bit 0
SCLi
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) Master mode
CKDIR = 0 (internal clock), CKPH = 1 (clock delayed)
STSPSEL bit
SCLi
Set to 1 by Set to 0 by
a program a program
Set to 1 by Set to 0 by
a program a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SDAi
Set STAREQ = 1
(start)
i = 0 to 2, 5 to 7
Set STPREQ=1
Start condition detection
(start) ^{Stop condition detection}
interrupt
interrupt
Figure 23.21 STSPSEL Bit Functions
23.3.3.3 Arbitration
Unmatching of the transmit data and SDAi pin input data is checked in synchronization with the rising
edge of SCLi. Use the ABC bit in the UiSMR register to select the point at which the ABT bit in the
UiRB register is updated. If the ABC bit is 0 (update per bit), the ABT bit is set to 1 at the same time
unmatching is detected during check, and is set to 0 when not detected. If the ABC bit is set to 1, if
unmatching is ever detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the
clock pulse of the 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit to 0
(undetected) after detecting acknowledge for the first byte, before transmitting/receiving the next
byte.
Setting the ALS bit in the UiSMR2 register to 1 (SDA output stop enabled) causes an arbitration-lost
to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT
bit is set to 1 (unmatching detected).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 534 of 791