M16C65 Datasheet, PDF (570/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.3.4 Transmit/Receive Clock
The transmit/receive clock is used to transmit/receive data as is shown in Figure 23.19.
The CSC bit in the UiSMR2 register is used to synchronize an internally generated clock (internal
SCLi) and an external clock supplied to the SCLi pin. If the CSC bit is set to 1 (clock synchronization
enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi
goes low, at which time the value of the UiBRG register is reloaded with and starts counting the low-
level intervals. If the internal SCLi changes state from low to high while the SCLi pin is low, counting
stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transmit/receive clock is equivalent to AND of the internal SCLi and the clock
signal applied to the SCLi pin. The transmit/receive clock works from a half cycle before the falling
edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal
clock for the transmit/receive clock.
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed low or freed from low-
level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the UiSMR4 register is set to 1 (enabled), SCLi output is turned off (placed in the
high-impedance state) when a stop condition is detected.
When the SWC2 bit in the UiSMR2 register is set to 1 (0 output), a low-level signal can be forcibly
output from the SCLi pin even while transmitting or receiving data. When the SWC2 bit is set to 0
(transmit/receive clock), a low-level signal output from the SCLi pin is cancelled, and the transmit/
receive clock is input and output.
If the SWC9 bit in the UiSMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the
UiSMR3 register is 1, the SCLi pin is fixed low at the falling edge of the clock pulse next to the 9th.
Setting the SWC9 bit to 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
23.3.3.5 SDA Output
The data written to bits 7 to 0 (D7 to D0) in the UiTB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDAi transmit output when IICM is 1 (I²C mode) and bits SMD2 to SMD0 in the
UiMR register are 000b (serial interface disabled).
Bits DL2 to DL0 in the UiSMR3 register allow addition of no delays or a delay of 2 to 8 UiBRG count
source clock cycles to the SDAi output.
Setting the SDHI bit in the UiSMR2 register to 1 (SDA output disabled) forcibly places the SDAi pin in
the high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi transmit/
receive clock. This is because the ABT bit may inadvertently be set to 1 (detected).
23.3.3.6 SDA Input
When the IICM2 bit is 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits 7 to 0 in the
UiRB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits 6 to 0 in the
UiRB register and the 8th bit (D0) is stored in bit 8 in the UiRB register. Even when the IICM2 bit is 1,
the same data as when the IICM2 bit is 0 can be read, provided the CKPH bit is 1. To read the data,
read the UiRB register after the rising edge of 9th bit of the clock.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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