M16C65 Datasheet, PDF (463/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
20. Real-Time Clock
20.5 Notes on Real-Time Clock
20.5.1 Starting and Stopping Count
Real-time clock has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which
indicates count start or stop. Bits TSTART and TCSTF are in the RTCCR1 register.
Real-time clock starts counting and the TCSTF bit becomes 1 (count starts) when the TSTART bit is set
to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit becomes 1 after
setting the TSTART bit to 1. During this time, do not access registers associated with real-time clock ⁽¹⁾
other than the TCSTF bit.
Also, real-time clock stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit
becomes 0 (count stops). It takes up to three cycles of the count source until the TCSTF bit becomes 0
after setting the TSTART bit to 0. During this time, do not access registers associated with real-time
clock other than the TCSTF bit.
Note:
1. Registers associated with real-time clock: RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR1,
RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR.
20.5.2 Register Setting (Time Data etc.)
Write to the following registers or bits while real-time clock is stopped.
• Registers RTCSEC, RTCMIN, RTCHR, RTCWK, and RTCCR2
• Bits H12H24 and RTCPM in the RTCCR1 register
• Bits RCS0 to RCS4 in the RTCCSR register
Real-time clock is stopped when bits TSTART and TCSTF in the RTCCR1 register are 0 (real-time
clock stopped).
Also, set all above-mentioned registers and bits (immediately before real-time clock count starts) before
setting the RTCCR2 register.
Figure 20.4 shows Time and Day Change Procedure (No Compare Mode or Compare 1 Mode), and
Figure 20.5 shows Time and Day Change Procedure (Compare 2 Mode or Compare 3 Mode).
20.5.3 Register Setting (Compare Data)
Write to the following registers when the BSY bit in the RTCSEC register is 0 (not while data is
updated).
• Registers RTCCSEC, RTCCMIN, and RTCCHR
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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