M16C65 Datasheet, PDF (616/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.2.6 I2C0 Start/Stop Condition Control Register (S2D0)
I2C0 Start/Stop Condition Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S2D0
Address
02B5h
Bit Symbol
Bit Name
SSC0
Function
After Reset
0001 1010b
RW
RW
SSC1
RW
SSC2
Start/stop condition setting bit
Refer to "SSC4 to SSC0 (Start/Stop
Condition Setting Bit)" in the same page
RW
SSC3
RW
SSC4
RW
SIP
SCL/SDA interrupt pin polarity 0: Falling edge
select bit
1: Rising edge
RW
SIS
SCL/SDA interrupt pin select bit
0: SDAMM
1: SCLMM
RW
STSPSEL
Start/stop condition generation 0: Short setup/hold time mode
select bit
1: Long setup/hold time mode
RW
SSC4-SSC0 (Start/Stop Condition Setting Bit) (b4-b0)
Bits SSC4 to SSC0 select the start/stop condition detect condition (SCL open time, setup time, hold
time) in standard clock mode. Refer to 25.3.7 “Start Condition and Stop Condition Detection”.
Do not set odd values or 00000b to bits SSC4 to SSC0.
SIP (SCL/SDA Interrupt Pin Polarity Select Bit) (b5)
SIS (SCL/SDA Interrupt Pin Select Bit) (b6)
The IR bit in the SCLDAIC register is set to 1 (interrupt requested) when the I²C interface detects the
edge selected by the SIP bit for the pin signal selected by the SIS bit. Refer to 25.4 “Interrupts”.
STSPSEL (Start/Stop Condition Generation Select Bit) (b7)
Refer to Table 25.13 “Setup/Hold Time for Start/Stop Condition Generation”.
If the fVIIC frequency is more than 4 MHz, set the STSPSEL bit to 1 (long mode).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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