M16C65 Datasheet, PDF (196/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11.2.1 Chip Select Control Register (CSR)
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSR
Address
0008h
Bit Symbol
Bit Name
CS0 CS0 output enable bit
CS1 CS1 output enable bit
CS2 CS2 output enable bit
CS3 CS3 output enable bit
CS0W CS0 wait bit
CS1W CS1 wait bit
CS2W CS2 wait bit
CS3W CS3 wait bit
After Reset
01h
Function
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
0 : Wait state
1 : No wait state
11. Bus
RW
RW
RW
RW
RW
RW
RW
RW
RW
CSiW (CSi Wait Bit) (b7-b4) (i = 0 to 3)
Set the CSiW bit to 0 (wait state) under the following conditions:
• The RDY signal is used in the area indicated by CSi.
• Multiplexed bus is used in the area indicated by CSi.
• The PM17 bit in the PM1 register is 1 (wait state).
When the CSiW bit is 0 (wait state), the number of wait states can be selected using bits CSEi1W to
CSEi0W in the CSE register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 161 of 791