M16C65 Datasheet, PDF (209/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
11.3.5.9 External Bus Status When Internal Area is Accessed
Table 11.10 lists the External Bus Status When an Internal Area is Accessed. Figure 11.5 shows the
Typical Bus Timings When Accessing SFRs.
Table 11.10 External Bus Status When an Internal Area is Accessed
Item
A0 to A19
D0 to D15 Read
Write
RD, WR, WRL, WRH
BHE
CS0 to CS3
ALE
SFR Accessed
Address output
High-impedance
Data output
RD, WR, WRL, WRH output
BHE output
High-level output
Low-level output
Internal ROM or RAM Accessed
Maintain the last accessed address of external
area or SFR
High-impedance
Undefined
High-level output
Maintain the last accessed status of external
area or SFRs
High-level output
Low-level output
(1) 1 Wait State (1φ + 1φ)
BCLK
Address
High
CSi
Data
RD
WR, WRL, WRH
Bus cycle = 2φ
A
WD
Bus cycle = 2φ
A
RD
(2) 2 Wait States (1φ + 2φ)
BCLK
Address
High
CSi
Data
RD
WR, WRL, WRH
Bus cycle = 3φ
A
WD
i = 0 to 3
A : Address RD : Read data WD : Write data
Figure 11.5 Typical Bus Timings When Accessing SFRs
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 174 of 791
Bus cycle = 3φ
A
RD