M16C65 Datasheet, PDF (286/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.13 Notes on Interrupts
14.13.1 Reading Address 00000h
Do not read the address 00000h by a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from address
00000h during the interrupt sequence. At this time, the IR bit of the accepted interrupt is cleared to 0.
If the address 00000h is read by a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to 0. Thus, some problems may be caused: interrupts may be
canceled, and an unexpected interrupt request may be generated.
14.13.2 SP Setting
Set a value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after
reset. Therefore, if an interrupt is accepted before setting a value in the SP (USP, ISP), the program
may go out of control.
Especially when using the NMI interrupt, set a value in the ISP at the beginning of the program. For the
first instruction after reset only, all interrupts including the NMI interrupt are disabled.
14.13.3 NMI Interrupt
• When the NMI interrupt is not used, set the PM24 bit in the PM2 register to 0 (NMI interrupt dis-
abled).
• Stop mode cannot be entered while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin
is low. When input on the NMI pin is low, the CM10 bit in the CM1 register is fixed to 0.
• Do not enter wait mode while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin is low
because the CPU clock remains active even though the CPU stops, and therefore, the current con-
sumption of the chip does not drop. In this case, the normal condition is restored by the next inter-
rupt generated.
• Set the low- and high-level durations of the input signal to the NMI pin to 2 CPU clock cycles + 300
ns or more.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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