M16C65 Datasheet, PDF (67/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen
compose a register bank. There are two sets of register banks.
b31
R2
R3
b15
b8 b7
b0
R0H(high-order bitsof R0) R0L(low-order bitsof R0)
R1H(high-order bitsof R1) R1L(low-order bitsof R1)
R2
R3
A0
A1
FB
Data Registers ⁽¹⁾
Address Registers ⁽¹⁾
Frame Base Registers ⁽¹⁾
b19
b15
b0
INTBH
INTBL
INTBH is the 4 high-order bits of the INTB register
and INTBL is 16 low-order bits.
b19
b0
PC
Interrupt Table Register
Program Counter
b15
b0
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
SB
Static Base Register
b15
b0
FLG
Flag Register
b15
IPL
b8 b7
b0
U I OB S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic and logic operations. R0 and R1 can
be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data
registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). Also, R3R1 is the
combination of R3 and R1.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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