M16C65 Datasheet, PDF (611/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
ES0 (I2C bus Interface Enable Bit) (b3)
The ES0 bit enables the I²C interface.
When the ES0 bit is set to 0, the I²C interface status becomes as follows.
• Pins SDAMM and SCLMM: I/O port or other peripheral pins
• Write disable to the S00 register
• I²C-bus system clock (hereinafter called fVIIC) stops
• S10 register
ADR0 bit: 0 (general call not detected)
AAS bit: 0 (slave address not matched)
AL bit: 0 (arbitration lost not detected)
PIN bit: 1 (no I²C-bus interrupt request)
BB bit: 0 (bus free)
TRX bit: 0 (receive mode)
MST bit: 0 (slave mode)
• Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches)
• TOF bit in the S4D0 register: 0 (timeout not detected)
ALS (Data Format Select Bit) (b4)
The ALS bit is enabled in slave mode. When the ALS bit is 0 (addressing format), the slave address
match detection is performed.
When any of the slave address stored into bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is
compared and matched with the calling address by a master, or when a general call address is
received, the IR bit in the IICIC register becomes 1 (interrupt requested).
When the ALS bit is 1 (free format), the slave address match detection is not performed. Therefore, the
IR bit in the IICIC register becomes 1 (interrupt requested), regardless of the calling address by a
master.
IHR (I2C bus Interface Reset Bit) (b6)
The IHR bit resets the I²C interface if a difficulty in transmission/reception is encountered. When the
ES0 bit in the S1D0 register is 1 (I²C interface enabled) and then the IHR bit is set to 1 (reset), the I²C
interface becomes as follows.
• S10 register
ADR0 bit: 0 (general call not detected)
AAS bit: 0 (slave address not matched)
AL bit: 0 (arbitration lost not detected)
PIN bit: 1 (No I²C-bus interrupt request)
BB bit: 0 (bus free)
TRX bit: 0 (receive mode)
MST bit: 0 (slave mode)
• Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches)
• TOF bit in the S4D0 register: 0 (timeout not detected)
When the IHR bit is set to 1, the I²C interface is reset and the IHR bit becomes 0 automatically. It takes
maximum of 2.5 fVIIC cycles to complete reset sequence.
Figure 25.3 shows Reset Timing of I²C Interface.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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