M16C65 Datasheet, PDF (568/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.3.1 Detection of Start and Stop Conditions
Whether a start or a stop condition has been detected is determined.
A start condition detect interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition detect interrupt request is generated when
the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition detect interrupts share an interrupt control register and vector,
check the BBS bit in the UiSMR register to determine which interrupt source is requesting the
interrupt.
3 to 6 cycles < setup time ⁽¹⁾
3 to 6 cycles < hold time ⁽¹⁾
SCLi
SDAi
(Start condition)
SDAi
(Stop condition)
Setup time
Hold time
i = 0 to 2, 5 to 7
When the PCLK1 bit in the PCLKR register is 1, this is the cycle count of f1SIO,
and the PCLK1 bit is 0, the cycle count of f2SIO.
Figure 23.20 Detection of Start and Stop Conditions
23.3.3.2 Output of Start and Stop Conditions
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to
1 (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start).
The output procedure is as follows.
(1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (output).
The functions of the STSPSEL bit are shown in Table 23.19 and Figure 23.21.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 533 of 791