M16C65 Datasheet, PDF (599/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
24. Serial Interface SI/O3 and SI/O4
24.3.6 External Clock
When the SMi6 bit in the SiC register is set to 0, data is transmitted/received using external clock.
The external clock is used as transmit/receive clock, the SOUTi output level from when the SMi3 bit in
the SiC register is set to 1 (SI/Oi enabled) and SMi2 bit is set to 0 (SOUTi output enabled) to when the
first data is output can be selected by the SMi7 bit in the SiC register. Refer to 24.3.8 “Function for
Setting SOUTi Initial Value”.
Transmission/reception starts with the external clock after writing the transmit data into the SiTRR
register.
The data written into the SiTRR register is shifted every time the external clock is input. When
completing data transmission/reception of the 8th bit, read or write into the SiTRR register before
inputting the clock for the next data transmission/reception.
Figure 24.6 shows SI/Oi Operation Timing (External Clock).
If the SMi4 bit is set to 0, write into the SiTRR register
when CLKi input is the high level .
CLKi input
Write signal to the
SiTRR register
SOUTi output
SINi input
D0
D1
D2
D0
D1
D2
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
IR bit in the SiIC
register
i = 3, 4
The above diagram applies under the following conditions.
In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is output at
falling edge of transmit/receive clock and receive data is input at rising edge), SMi5 = 0 (LSB first), SMi6 = 0 (external clock)
Figure 24.6 SI/Oi Operation Timing (External Clock)
When the SMi6 bit in the SiC register is set to 0 (external clock), write into the SiTRR register and SMi7
bit in the SiC register under the following conditions:
• When the SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/
receive clock and receive data is input at rising edge): CLKi input is high level.
• When the SMi4 bit is set to 1 (transmit data is output at rising edge of transmit/receive clock and
receive data is input at falling edge): CLKi input is low level.
24.3.7 SOUTi Pin
The SOUTi pin state can be selected by bits SMi2 and SMi3 in the SiC register.
Table 24.4 lists SOUTi Pin State.
Table 24.4 SOUTi Pin State
Bit Setting
SiC register
SMi2
SMi3
0
0
1
1
0/1
SOUTi Pin State
I/O port or another peripheral function
SOUTi output
High-impedance
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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