M16C65 Datasheet, PDF (595/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
24. Serial Interface SI/O3 and SI/O4
24.3 Operations
24.3.1 Basic Operations
SI/Oi transmits and receive data simultaneously. The SiTRR register is not divided into the register for
transmission/reception and buffer. Write transmit data into the SiTRR register while transmission/
reception stops. Read receive data from the SiTRR register while transmission/reception stops.
24.3.2 CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transmit/receive clock. Figure 24.2
shows Polarity of Transmit/Receive Clock.
.
(1) When the SMi4 bit in the SiC register = 0
CLKi
SOUTi
High level is output if not
transmitting/receiving data
D0 D1 D2 D3 D4 D5 D6 D7
SINi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the SMi4 bit = 1
CLKi
Low level is output if not
transmitting/receiving data
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
SINi
D0 D1 D2 D3 D4 D5 D6 D7
i = 3, 4
Notes:
The above diagram applies under the following conditions.
1. The SMi5 bit in the SiC register is 0 (LSB first).
2. The SMi6 bit in the SiC register is 1 (internal clock).
3. The SM26 bit or SM27 bit in the S32C2 register is 1 (SOUTi output retains last bit level)
Figure 24.2 Polarity of Transmit/Receive Clock
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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