M16C65 Datasheet, PDF (602/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
24. Serial Interface SI/O3 and SI/O4
24.5 Notes on Serial Interface SI/O3 and SI/O4
24.5.1 SOUTi Pin Level When SOUTi Output Disabled
When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin goes to high-
impedance state regardless of which function of the pin is being used.
24.5.2 External Clock Control
The data written into the SiTRR register is shifted every time the external clock is input. When
completing data transmission/reception of the 8th bit, read or write into the SiTRR register before
inputting the clock for the next data transmission/reception.
24.5.3 Register Access When Using External Clock
When the SMi6 bit in the SiC register is set to 0 (external clock), write into the SMi7 bit in the SiC
register and the SiTRR register under the following conditions:
• When the SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/
receive clock and receive data is input at rising edge): CLKi input is high level.
• When the SMi4 bit in the SiC register is set to 1 (transmit data is output at rising edge of transmit/
receive clock and receive data is input at falling edge): CLKi input is low level.
24.5.4 SiTRR Register Access
Write transmit data into the SiTRR register while transmission/reception stops. Read receive data from
the SiTRR register while transmission/reception stops.
The IR bit in the SiIC register becomes 1 (interrupt request) during output of the 8th bit.
If the SM26 bit (SOUT3) or SM27 bit (SOUT4) in the S32C2 register is set to 0 (high-impedance after
transmission), SOUTi pin becomes high-impedance when the transmit data is written into the SiTRR
register immediately after an interrupt request is generated, and hold time of the transmit data becomes
shorter.
24.5.5 Pin Function Switch When Using Internal Clock
If the SMi3 bit in the SiC register (i = 3, 4) changes from 0 (I/O port) to 1 (SOUTi output, CLK function)
when setting the SMi2 bit to 0 (SOUTi output) and the SMi6 bit to 1 (internal clock), SOUTi initial value
set to the SOUTi pin by the SMi7 bit may be output about for 10 ns. After that, the SOUTi pin becomes
high-impedance.
If the output level from the SOUTi pin when the SMi3 bit changes from 0 to 1 becomes a problem, set
the SOUTi initial value by the SMi7 bit.
24.5.6 Operation After Reset When Selecting External Clock
When the SMi6 bit in the SiC register is set to 0 (external clock) after reset, the IR bit in the SiIC register
becomes 1 (interrupt request) by inputting the external clock for 8 bits to the CLKi pin. This will also
happen even when the SMi3 bit in the SiC register is 0 (serial interface disabled) or before the value is
written into the SiTRR register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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