M16C65 Datasheet, PDF (649/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.10.5 Slave Transmission
The slave transmission is described in this section. The initial settings described in 25.3.10.1 “Initial
Setting” are assumed to be completed. Figure 25.20 shows the example of slave transmission. The
following programs (A) to (B) are executed at the (A) and (B) in Figure 25.20, respectively.
S: Start condition
P: Stop condition
m
S
Slave address
(7 bits)
A: ACK
A: NACK
R: Read
W: Write
s
m
RA
Data
(8 bits)
A
m: Master outputs to SDA
s: Slave outputs to SDA
s
m
Data
(8 bits)
AP
SCLMM
SDAMM
IR bit in the IICIC
register
Set to 0 by interrupt request acceptance or by program
(A) Start of slave transmission _{(B) Data transmission}
Stop condition
Figure 25.20 Example of Slave Transmission
(A) Start of slave transmission
(In I²C-bus interrupt routine)
(1) Check the content of the S10 register. When the TRX bit is set to 1, the I²C interface is in slave-
transmitter mode.
(2) Write a transmit data to the S00 register
(B) Data transmission
(In I²C-bus interrupt routine)
(1) Write a transmit data to the S00 register
Write a dummy data to the S00 register even if an interrupt occurs at an ACK clock of the last transmit
data. When the S00 register is written, the SCLMM pin becomes high-impedance.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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