M16C65 Datasheet, PDF (813/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
31. Precautions
31.21.2 UART (Clock Asynchronous Serial I/O) Mode
31.21.2.1 Transmission/Reception
When the RTS function is used with an external clock, the RTSi pin (i = 0 to 2, 5 to 7) outputs a low-
level signal, which informs the transmitting side that the MCU is ready for a receive operation. The
RTSi pin outputs a high-level signal when a receive operation starts. Therefore, a transmit timing and
receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting
side. The RTS function is disabled when an internal clock is selected.
31.21.2.2 Transmission
When an external clock is selected, the following conditions must be met while the external clock is
held high when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is 0 (transmit data output at the
falling edge and receive data input at the rising edge of the transmit and receive clock), or while the
external clock is held low when the CKPOL bit is 1 (transmit data output at the rising edge and
receive data input at the falling edge of the transmit and receive clock).
• The TE bit in the UiC1 register is 1 (transmission enabled).
• The TI bit in the UiC1 register is 0 (data present in the UiTB register).
• When CTS function is selected, input on the CTSi pin is low.
31.21.3 Special Mode 1 (I²C Mode)
31.21.3.1 Generation of Start and Stop Conditions
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register (i = 0
to 2, 5 to 7) to 0 and wait for more than half cycle of the transmit and receive clock. Then set each
condition generation bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1.
31.21.3.2 IR Bit
Set the following bits first, and then set the IR bit in the UARTi interrupt control registers to 0 (interrupt
not requested).
Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register,
the IICM2 bit in the UiSMR2 register, the CKPH bit in the UiSMR3 register
31.21.4 Special Mode 4 (SIM Mode)
After reset, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1
register to 1 (transmission completed) and 1 (error signal output), respectively. Therefore, when using
SIM mode, make sure to set the IR bit to 0 (interrupt not requested) after setting these bits.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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