M16C65 Datasheet, PDF (204/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
Example 1
Accessing the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi.
The address bus and chip select signal both change state between these
two cycles.
Access to the external Access to the external
area indicated by CSi area indicated by CSj
Example 2
Accessing the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi.
The chip select signal changes state but the address bus does not change
state.
Access to the external Access to the internal
area indicated by CSi ROM or internal RAM
BCLK
Read signal
Data bus
Address bus
CSi
CSj
Data Data
Address Address
BCLK
Read signal
Data bus
Address bus
CSi
Data
Address
Example 3
Accessing the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi.
The address bus changes state but the chip select signal does not change
state.
Example 4
Not accessing any area (no instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi.
Neither the address bus nor the chip select signal changes state between these
two cycles.
Access to the external Access to the same
area indicated by CSi external area
Access to the external
area indicated by CSi
No access
BCLK
Read signal
Data bus
Address bus
CSi
Data Data
Address Address
BCLK
Read signal
Data bus
Address bus
CSi
Data
Address
Note:
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip
select bus cycle may be extended to more than two cycles depending on the combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states.
i = 0 to 3, j = 0 to 3 (not including i, however)
Figure 11.2 Examples of Address Bus and CSi Signal Output in 1-Mbyte Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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