M16C65 Datasheet, PDF (773/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
Table 30.22 Setting of Standard Serial I/O Mode 2
Signal
CNVSS
EPM
RESET
CE
P6_5/CLK1
Input Level
VCC1
VSS
VSS → VCC1
VCC2
VSS
30. Flash Memory
TXD output
Monitor output
RXD intput
VCC1
MCU
VCC2
P6_5/CLK1
P6_7/TXD1
P6_4/RTS1
P6_6/RXD1
P5_0 (CE)
P5_5 (EPM)
VCC1
CNVSS
Reset input
RESET
User reset signal
Note:
1. In this example, modes are switched between single-chip mode and standard serial I/O
mode by controlling the CNVSS input with a switch.
Figure 30.21 Circuit Application in Standard Serial I/O Mode 2
30.9.6 Parallel I/O Mode
In parallel I/O mode, program ROM 1, program ROM 2, and data flash can be rewritten using a parallel
programmer supporting the M16C/65 Group. Contact the parallel programmer manufacturer for more
information. Refer to the user’s manual included with your parallel programmer for instructions.
30.9.6.1 ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
I/O mode. Refer to 30.4 “Optional Function Select Address 1 (OFS1)”. The OFS1 address is located
in block 0 in program ROM 1.
The ROM code protect function is enabled when the ROMCP1 bit is set to 0.
To cancel ROM code protect, erase block 0 including the OFS1 address using standard serial I/O
mode or CPU rewrite mode.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 738 of 791