M16C65 Datasheet, PDF (594/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
24.2.4 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4)
24. Serial Interface SI/O3 and SI/O4
SI/Oi Bit Rate Register (i = 3, 4)
b7
b0
Symbol
S3BRG
S4BRG
Address
0273h
0277h
Function
SiBRG divides the count source by n + 1 where n = set
value
After Reset
Undefined
Undefined
Setting Range
RW
00h to FFh
WO
Use MOV instruction to write into the SiBRG register.
Write into the SiBRG register after setting bits SMi1 to SMi0 in the SiC register and while serial interface
is neither transmitting nor receiving.
24.2.5 SI/O3, 4 Control Register 2 (S34C2)
SI/O3, 4 Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
S34C2
Address
0278h
After Reset
00XX X0X0b
Bit Symbol
Bit Name
Function
RW
—
(b0)
Reserved bit
Set to 0
RW
—
(b1)
No register bit. If necessary, set to 0. Read as undefined value
—
SM22
SI/O3, SI/O4 before-division 0: f1
clock select bit
1: fOCO-F
RW
—
(b5-b3)
No register bits. If necessary, set to 0. Read as undefined value
—
SOUT3 state after transmission
SM26 SOUT3 output control bit 0 : High-impedance
RW
1 : Last bit level retained
SOUT4 state after transmission
SM27 SOUT4 output control bit 0 : High-impedance
RW
1 : Last bit level retained
SM22 (SI/O3, SI/O4 Before-division Clock Select Bit) (b2)
Set the SM22 bit while transmission/reception of SI/O3 and SI/O4 stops.
Set the SM22 bit before setting other registers associated with SI/O3 and SI/O4. After changing the
SM22 bit, set other registers associated with SI/O3 and SI/O4 again.
SM26 (SOUT3 Output Control Bit) (b6)
SM27 (SOUT4 Output Control Bit) (b7)
Bits SM26 and SM27 are valid when the SMi6 bit in the SiC register is set to 1 (internal clock). Set the
SMi3 bit in the SiC register to 1 (serial interface enabled) after setting bits SM26 and SM27.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 559 of 791