M16C65 Datasheet, PDF (296/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
15. Watchdog Timer
15.4 Operations
15.4.1 Count Source Protection Mode Disabled
The CPU clock is used as the watchdog timer count source when count source protection mode is
disabled.
Table 15.3 lists Watchdog Timer Specifications (Count Source Protection Mode Disabled).
Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Disabled)
Item
Count source
Count operation
Cycles
Specification
CPU clock
Decrement
When the CM07 bit in the CM0 register is 0 (main clock, PLL clock, fOCO-F, fOCO-S):
-P---r--e----s---c---a---l--e---r---d----i-v---i-d----e-----v---a---l--u---e-----(--n---)----^×-----w----a---t--c---h---d----o---g-----t--i-m-----e---r----c---o---u----n---t---v---a----l-u---e-----(--3----2---7---6----8---) ⁽¹⁾
CPU clock
n: 16 or 128 (selected by the WDC7 bit in the WDC register)
ex.) When CPU clock frequency is 16 MHz and the prescaler division rate is 16, the
watchdog timer cycle is approximately 32.8 ms.
When the CM07 bit is 1 (sub clock):
P----r--e----s---c---a---l-e----r---d----i-v---i-d----e-----v---a---l--u---e-----(--2---)----×_{----w-----a---t--c---h---d----o---g-----t--i-m-----e---r----c---o---u----n---t---v---a----l-u---e-----(--3----2---7---6----8---) (1)}
CPU clock
Watchdog timer
counter initial value
setting
• Reset (Refer to 6. “Resets”.)
• Write 00h, and then FFh to the WDTR register.
• Underflow
Count start
conditions
Set the WDTON bit in the OFS1 address to select the watchdog timer operation
after reset.
• WDTON bit is 1 (watchdog timer is in stop state after reset)
The watchdog timer and prescaler stop after reset and count starts by writing to
the WDTS register.
• WDTON bit is 0 (watchdog timer starts automatically after reset)
The watchdog timer and prescaler start counting automatically after reset.
Count stop
conditions
• Stop mode
• Wait mode
• Bus hold
(Count resumes from the hold value after exiting.)
Operation when
timer underflows
• PM12 bit in the PM1 register is 0
Watchdog timer interrupt
• PM12 bit in the PM1 register is 1
Watchdog timer reset (See 6.4.8 “Watchdog Timer Reset”.)
Notes:
1.
Writing 00h and then FFh to the WDTR register initializes the watchdog timer, but not the
prescaler. Thus, some errors in the watchdog timer period may be caused by the prescaler. The
prescaler is initialized after reset.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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