M16C65 Datasheet, PDF (610/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25.2.4 I2C0 Control Register (S1D0)
25. Multi-Master I²C-bus Interface
I2C0 Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
S1D0
Address
02B3h
After Reset
00X0 0000b
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
BC0
0 0 0: 8
RW
0 0 1: 7
0 1 0: 6
BC1
Bit counter (number of
transmitted/received bits)
0 1 1: 5
1 0 0: 4
RW
1 0 1: 3
BC2
1 1 0: 2
RW
1 1 1: 1
ES0
I2C bus interface enable bit
0: Disabled
1: Enabled
RW
ALS Data format select bit
0: Addressing format
1: Free data format
RW
—
(b5)
Reserved bit
Set to 0.
RW
IHR I2C-bus interface reset bit
0: reset is deasserted (automatically)
1: reset
RW
TISS
I2C-bus interface pin input
level select bit
0: I²C-bus input
1: SMBus input
RW
BC2-BC0 (Bit Counter) (b2-b0)
Bits BC2 to BC0 become 000b (8 bits) when start or stop condition is detected.
When the ACKCLK bit in the S20 register is 0 (no ACK clock), and data for the number of bits selected
by bits BC2 to BC0 is transmitted or received, bits BC2 to BC0 become 000b again.
When the ACKCLK bit in the S20 register is 1 (ACK clock), data for the number of bits selected and an
ACK is transmitted or received, bits BC2 to BC0 become 000b again.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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