M16C65 Datasheet, PDF (312/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
16.3.4 DMAC Transfer Cycles
The number of DMA transfer cycles can be calculated as shown below.
Table 16.8 lists the DMAC Transfer Cycles, and Table 16.9 and Table 16.10 list coefficients j and k.
Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k
Table 16.8 DMAC Transfer Cycles
Transfer Unit Bus Width
Access
Address
8-bit transfers
(DMBIT = 1)
16-bit transfers
(DMBIT = 0)
16-bit
(BYTE = low)
8-bit
(BYTE = high)
16-bit
(BYTE = low)
8-bit
(BYTE = high)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Single-Chip Mode
No. of Read
Cycles
1
1
N/A
N/A
1
2
N/A
N/A
No. of Write
Cycles
1
1
N/A
N/A
1
2
N/A
N/A
Memory Expansion Mode
Microprocessor Mode
No. of Read No. of Write
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
Table 16.9 Coefficients j and k (1/2)
j
k
Notes:
1.
2.
Internal Area
Internal ROM, RAM
SFR
No wait
states
1 wait state 2 wait states
Wait states
(2)
(2)
1
2
2
3
1
2
2
3
External Area
Multiplex bus
Wait states ⁽¹⁾
1 wait state 2 wait states 3 wait states
3
3
4
3
3
4
Depends on the set value of the CSE register.
Depends on the set value of the PM20 bit in the PM2 register.
Table 16.10 Coefficients j and k (2/2)
External Area
Separate bus ⁽¹⁾
No wait
states
Wait states ⁽²⁾
1wait state
(1φ + 1φ)
2 wait states 3 wait states
(1φ + 2φ) (1φ + 3φ)
2φ + 3φ
2φ + 4φ
3φ + 4φ
4φ + 5φ
j
1
2
3
4
5
6
7
9
k
2
2
3
4
5
6
7
9
Notes:
1. When recovery cycle inserted is selected at bits EWR1 and EWR0 in the EWR register, add the
recovery cycle.
2. Depends on the set values of registers CSE and EWC.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 277 of 791