M16C65 Datasheet, PDF (361/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
Table 17.17 Registers and the Setting in Programmable Output Mode ⁽¹⁾
Register
Bit
Setting
PCLKR
PCLK0
Select the count source.
CPSRF
CPSR
Write a 1 to reset the clock prescaler.
TCKDIVC0
TCDIV00
Select a clock used prior to timer AB frequency dividing.
PWMFS
PWMFSi
Set to 1.
TACS0 to TACS2 7 to 0
Select the count source.
TAPOFS
POFSi
Select the output polarity.
TAi1
7 to 0
Set a low-level pulse width. ⁽²⁾
TABSR
TAiS
Set to 1 when starting counting.
Set to 0 when stopping counting.
ONSF
TAiOS
Set to 0.
TAZIE
Set to 0.
TAiTGH to TAiTGL Select a count trigger.
TRGSR
TAiTGH to TAiTGL Select a count trigger.
UDF
TAiUD
Set to 0.
TAiP
Set to 0.
TAi
7 to 0
Set a high-level pulse width. ⁽²⁾
TAiMR
7 to 0
Refer to the following TAiMR register.
i = 1, 2, and 4
Notes:
1. This table does not describe a procedure.
2. This applies when the POFSi bit in the TAPOFS register is 0.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 326 of 791