M16C65 Datasheet, PDF (676/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
26. Consumer Electronics Control (CEC) Function
26.3.5.4 Reception Examples
Figure 26.9 shows a Reception Example and Figure 26.10 shows a Reception Example (Change
from Error Low Pulse Output Disabled to Enabled When an Error Occurs).
When a receive error occurs, the CRERRFLG bit in the CECFLG register becomes 1 (receive error).
If a reception ends due to the error during the reception, set the CRXDEN bit in the CECC3 register
to 0 (receive disabled). When the CRXDEN bit is set to 0, the CRERRFLG bit becomes 0. To restart
the reception, set the CRXDEN bit to 0 (reception disabled), and then set the CRXDEN bit to 1
(reception enabled) after waiting for one or more cycles of the count source.
CEC
Header block
Data block
ST
H7 H6 ^{. . . .} H1 H0 EOM ACK D7 D6 ^{. . . .} D1 D0 EOM ACK
CRXDEN bit
CRFLG bit
CRSTFLG bit
CRD8FLG bit
IR bit
Set to 0 by acceptance of an
interrupt request or by a program
Set to 0 by acceptance of an
interrupt request or by a program
CCRB1 register
Undefined
Header block data
Data block data
CCRBE bit
CCRBAI bit
Undefined
Undefined
Header block EOM
Data block EOM
Header block ACK
CRXDEN bit: Bit in the CECC3 register
Bits CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register
IR bit: Bit in the CEC2IC register
Bits CCRBE and CCRBAI: Bits in the CCRB2 register
The above diagram applies under the following conditions.
y The CFIL bit in the CICC2 register is set to 0 (filter disabled).
y The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled).
y The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled).
y The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled).
Data block ACK
Figure 26.9 Reception Example
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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