M16C65 Datasheet, PDF (200/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
11.3 Operations
11.3.1 Common Specifications of Internal Bus and External Bus
11.3.1.1 Reference Clock
Both the internal and external buses operate based on the BCLK. However, the area accessed and
wait states affect bus operation. Refer to 11.3.2.1 “Software Wait States of the Internal Bus” and
11.3.5.10 “Software Wait States” for details.
11.3.1.2 Bus Hold
Both the internal and external buses are in a hold state under the following conditions:
• Rewriting the flash memory in EW1 mode while auto-programming or auto-erasing
• Inputting a low-level signal to the HOLD pin in memory expansion mode or microprocessor mode
When the bus is in hold state, the following occur:
• CPU is stopped
• DMAC is stopped
• Watchdog timer is stopped when the CSPRO bit in the CSPR register is 0 (count source protection
mode disabled)
Bus use priority is given to bus hold, DMAC, and CPU in descending order. However, if the CPU is
accessing an odd address in word units, the DMAC cannot gain control of the bus between two
separate accesses.
Bus Hold > DMAC > CPU
Figure 11.1 Bus Use Priority
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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