M16C65 Datasheet, PDF (117/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
7.2.5 Voltage Monitor 0 Circuit Control Register (VW0C)
7. Voltage Detector
Voltage Monitor 0 Circuit Control Register
b7 b6 b5 b4 b3 b2 b1 b0
11
0
Symbol
VW0C
Address
002Ah
After Reset
1100 1X10b ⁽¹⁾
1100 1X11b ⁽²⁾
Bit Symbol
Bit Name
Function
RW
VW0C0
Voltage monitor 0 reset
enable bit
0 : Disabled
1 : Enabled
RW
VW0C1
Voltage monitor 0 digital filter 0 : Enable digital filter
disable mode select bit
1 : Disable digital filter
RW
—
(b2)
Reserved bit
Set to 0.
Read as undefined value
RW
—
(b3)
Reserved bit
Read as undefined value
RO
VW0F0
b5 b4
0 0 : fOCO-S divided by 1
Sampling clock select bit
0 1 : fOCO-S divided by 2
RW
VW0F1
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
—
(b7-b6)
Reserved bits
Set to 1
RW
Notes :
1. When the LVDAS bit of address OFS1 is 1 at hardware reset
2. This value shows the value after any of the following resets:
- Voltage monitor 0 reset
- When the LVDAS bit of address OFS1 is 0 at hardware reset
- Power-on reset
Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing to the VW0C register.
This register does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop
detection reset, watchdog timer reset, or software reset.
VW0C0 (Voltage Monitor 0 Reset Enable Bit) (b0)
The VW0C0 bit is enabled when the VC25 bit in the VCR2 register is 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disabled) when the VC25 bit is 0 (voltage detection 0 circuit
disabled).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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