M16C65 Datasheet, PDF (214/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
(3) Bus cycle 3φ + 4φ
BCLK
Address
CSi
Read data
RD
Write data
WR, WRL, WRH
1 bus cycle = 7φ
A
(Note1)
RD
WD
(4) Bus cycle 4φ + 5φ
BCLK
Address
CSi
Read data
RD
Write data
WR, WRL, WRH
1 bus cycle = 9φ
A
WD
(Note1)
RD
i = 0 to 3
A : Address RD : Read data (input) WD : Write data (output)
Note:
1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level.
Figure 11.9 Typical Bus Timings Using Software Wait States (4/4)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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