M16C65 Datasheet, PDF (271/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.6.1 Fixed Vector Tables
The fixed vector tables are allocated to addresses from FFFDCh to FFFFFh. Table 14.5 lists the Fixed
Vector Tables. In the flash memory MCU version, the vector addresses (H) of fixed vectors are used for
the ID code check function and OFS1 address. For details, refer to 30.5 “Flash Memory Rewrite
Disable Function”.
Table 14.5 Fixed Vector Tables
Interrupt Source
Vector Table Addresses
Address (L) to Address (H)
Reference
Undefined instruction
(UND instruction)
FFFDCh to FFFDFh
M16C/60, M16C/20, M16C/
Tiny Series Software Manual
Overflow (INTO instruction)
FFFE0h to FFFE3h
BRK instruction ⁽²⁾
FFFE4h to FFFE7h
Address match
FFFE8h to FFFEBh
14.11 “Address Match
Interrupt”
Single-step ⁽¹⁾
FFFECh to FFFEFh
-
Watchdog timer,
FFFF0h to FFFF3h
oscillation stop and re-oscillation detection,
voltage monitor 1, voltage monitor 2
15. “Watchdog Timer”
8. “Clock Generator”
7. “Voltage Detector”
DBC ⁽¹⁾
FFFF4h to FFFF7h
-
NMI
FFFF8h to FFFFBh
14.9 “NMI Interrupt”
Reset
FFFFCh to FFFFFh
6. “Resets”
Notes:
1.
2.
Do not use this interrupt because it is provided exclusively for use by development tools.
If the content of address FFFE6h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
14.6.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register compose a relocatable vector
table area. Table 14.6 and Table 14.7 list the Relocatable Vector Tables. Setting an even address in the
INTB register results in the interrupt sequence being executed faster than setting an odd address.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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