M16C65 Datasheet, PDF (618/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
WIT (Data Receive Interrupt Enable Bit) (b1)
The WIT bit is enabled when the I²C interface is a master-receiver or slave-receiver.
The WIT bit has two functions.
• Select the I²C-bus interrupt timing when data is received. (write)
• Monitor the state of the internal WAIT flag. (read)
The WIT bit can select whether to generate an I²C-bus interrupt request at eighth clock (before ACK
clock) during the data reception.
When the ACKCLK bit in the S20 register is 1 (ACK clock) and the WIT bit is set to 1 (enable I²C-bus
interrupt at 8th clock), an I²C-bus interrupt request is generated at the eighth clock (before ACK clock).
Then, the PIN bit in the S10 register becomes 0 (interrupt requested).
When the ACKCLK bit in the S20 register is 0 (no ACK clock), write a 0 to the WIT bit to disable the I²C-
bus interrupt by data reception.
During data transmission and slave address reception, any interrupt request will not be generated at
the eighth clock (before ACK clock) regardless of the value written to the WIT bit.
Reads of the WIT bit returns the internal WAIT flag status.
The I²C-bus interrupt request is generated at the falling edge of the ninth clock (ACK clock) regardless
of the value written to the WIT bit. Then, the PIN bit in the S10 register becomes 0 (interrupt requested).
Therefore, read the internal WAIT flag status to determine whether the I²C-bus interrupt request is
generated at eighth clock (before ACK clock) or at the falling edge of the ACK clock.
When a 1 is written to the WIT bit to enable the I²C-bus interrupt by data reception, the internal WAIT
flag changes under the following condition.
Condition to become 0:
• The S20 register (ACKBIT bit) is written.
Condition to become 1:
• The S00 register is written.
During data transmission and slave address reception, the internal WAIT flag is 0 and the I²C-bus
interrupt request will be generated only at the falling edge of the ninth clock (ACK clock), regardless of
the value written to the WIT bit.
Table 25.6 lists an interrupt request generation timing and the conditions to restart transmission/
reception during data reception. Figure 25.4 shows Interrupt Request Generation Timing in Receive
Mode.
Table 25.6 Generating Interrupt Request and Restarting Transmission/Reception During Data
Reception
I²C-bus Interrupt Request Generation Timing Internal WAIT Flag Status
Conditions to Restart
Transmission/Reception
At the falling edge of 8th clock of data (before 1
Write to the ACKBIT bit in the
the ACK clock) ⁽¹⁾
S20 register ⁽³⁾
At the falling edge of 9th clock (ACK clock) ^{(2) 0}
Write to the S00 register
Notes:
1. See the timing of (1) on the IR bit in the IICIC register in Figure 25.4.
2. See the timing of (2) on the IR bit in the IICIC register in Figure 25.4.
3. Do not change the value of the bits other than ACKBIT bit in the S20 at this time. Also, do not
write to the S00 register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 583 of 791