M16C65 Datasheet, PDF (534/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.7 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7)
UARTi Transmit/Receive Control Register 0 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C0, U1C0, U2C0
U5C0, U6C0, U7C0
Address
024Ch, 025Ch, 026Ch
028Ch, 029Ch, 02ACh
After Reset
0000 1000b
0000 1000b
Bit Symbol
Bit Name
Function
RW
CLK0
CLK1
UiBRG count source select
bit
b1 b0
0 0 : f1SIO or f2SIO selected
0 1 : f8SIO selected
1 0 : f32SIO selected
1 1 : Do not set
RW
RW
Valid when CRD is 0
CRS CTS/RTS function select bit 0 : CTS function selected
RW
1 : RTS function selected
0 : Data present in transmit register
TXEPT
Transmit register empty flag
(transmission in progress)
1 : No data present in transmit register
RO
(transmission completed)
CRD CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
RW
NCH Data output select bit
CKPOL CLK polarity select bit
UFORM Bit order select bit
0 : Pins TXDi/SDAi and SCLi are CMOS
output
1 : Pins TXDi/SDAi and SCLi are N-channel
RW
open-drain output
0 : Transmit data is output at the falling
edge of transmit/receive clock and
receive data is input at the rising edge
1 : Transmit data is output at the rising
RW
edge of transmit/receive clock and
receive data is input at the falling edge
0 : LSB first
1 : MSB first
RW
CLK1 to CLK0 (UiBRG Count Source Select Bit) (b1-b0)
When bits CLK1 to CLK0 are 00b (f1SIO or f2SIO selected), select f1SIO or f2SIO by the PCLK1 bit in
the PCLKR register.
Set bits CLK1 to CLK0 after setting registers UCLKSEL0 and PCLKR.
If bits CLK1 to CLK0 are changed, set the UiBRG register.
CRS (CTS/RTS Function Select Bit) (b2)
CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register is 0 (CLK output is only from
CLK1) and the RCSP bit in the UCON register is 0 (CTS0/RTS0 not separated).
CRD (CTS/RTS Disable Bit) (b4)
When the CRD bit is 1 (CTS/RTS function disabled), the CTSi/RTSi pin can be used as an input/output
port.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 499 of 791