M16C65 Datasheet, PDF (627/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
PIN (I2C bus Interface Interrupt Request Bit) (b4)
The PIN bit function in read access is described as follows. See Table 25.10 “Functions Enabled by
Writing to the S10 Register” for the bit function in write access.
Condition to become 0:
• Slave address transmission is completed in master mode (including a case of detecting arbitration
lost).
• One-byte data transmission is completed (including a case of detecting arbitration lost).
• One-byte data reception is completed (the falling edge of 8th clock is detected when the ACKCKL
bit is set to 0. The falling edge of ACK clock when the ACKCKL bit is set to 1.).
• The WIT bit in the S3D0 register is set to 1 (I²C-bus interrupt enabled at 8th clock) and 1-byte data
is received (before ACK clock).
• In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and any of
the slave address stored into bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is matched with the
received slave address (slave address match).
• In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and the
general call address (0000000b) is received.
• In slave-receiver mode, the ALS bit in the S1D0 register is set to 1 (free format) and the slave
address reception is completed.
Condition to become 1:
• The S00 register is written.
• The S20 register is written (when the WIT bit is 1 and internal WAIT flag is 1).
• The ES0 bit in the S1D0 register is set to 0 (I²C interface disabled).
• The IHR bit in the S1D0 register is set to 1 (I²C interface reset).
The IR bit in the IICIC register is set to 1 (interrupt requested) as soon as the PIN bit is set to 0 (I²C-bus
interrupt requested). When the PIN bit is set to 0, the SCLMM pin output level is low.
However, the SCLMM pin output level does not become low when all the following conditions are met.
• In master mode, when arbitration lost is detected by a slave address, the ALS bit in the S1D0
register is 0 (addressing format), and the received address not 0000000b (general call) does not
match any of bits SAD6 to SAD0 in the registers S0D0 to S0D2.
• In master mode, when arbitration lost is detected by data, the ALS bit in the S1D0 register is 0
(addressing format), and the slave address not 0000000b (general call) does not match any of bits
SAD6 to SAD0 in the registers S0D0 to S0D2.
BB (Bus Busy Flag) (b5)
The BB bit function in read access is described as follows. See Table 25.10 “Functions Enabled by
Writing to the S10 Register” for the bit function in write access.
The BB bit indicates the state of the bus system, whether the bus is free or not. The BB bit changes
depending on the SCLMM and SDAMM input signals, regardless of master mode or slave mode.
Condition to become 0:
• Stop condition is detected.
• The ES0 bit in the S1D0 register is set to 0 (I²C interface disabled).
• The IHR bit in the S1D0 register is set to 1 (I²C interface reset).
Condition to become 1:
• Start condition is detected.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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