M16C65 Datasheet, PDF (274/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7 Interrupt Control
14.7.1 Maskable Interrupt Control
The settings of enabling/disabling the maskable interrupts and of the acceptance priority are explained
below. Note that these explanations do not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control
register to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated
by the IR bit in the corresponding interrupt control register.
14.7.1.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable
interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts.
14.7.1.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted, the IR bit is automatically set to 0 (interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
14.7.1.3 Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 14.8 lists the Settings of Interrupt Priority Levels and Table 14.9 lists the Interrupt Priority
Levels Enabled by IPL.
An interrupt request is accepted under the following conditions.
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent each other. In no case do they affect
one another.
Table 14.8 Settings of Interrupt Priority
Levels
Bits ILVL2 to ILVL0 Interrupt Priority Level
000b
Level 0 (interrupt disabled)
001b
Level 1
010b
Level 2
011b
Level 3
100b
Level 4
101b
Level 5
110b
Level 6
111b
Level 7
Priority
-
Low
High
Table 14.9
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Interrupt Priority Levels Enabled
by IPL
Enabled Interrupt Priority Levels
Level 1 and above are enabled
Level 2 and above are enabled
Level 3 and above are enabled
Level 4 and above are enabled
Level 5 and above are enabled
Level 6 and above are enabled
Level 7 and above are enabled
All maskable interrupts are disabled
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 239 of 791