M16C65 Datasheet, PDF (125/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
7. Voltage Detector
7.4.2.1 Voltage Monitor 0 Reset
When using voltage monitor 0 reset, set the VDSEL1 bit in the OFS1 address to 0 (Vdet0 is 2.85 V
(Vdet0_2)).
Table 7.6 lists Steps to Set Voltage Monitor 0 Reset Related Bits.
Table 7.6 Steps to Set Voltage Monitor 0 Reset Related Bits
Step
When Using the Digital Filter
When Not Using the Digital Filter
1
Set the CM14 bit in the CM1 register to 0 (125 -
kHz on-chip oscillator enabled).
2 Wait for digital filter sampling clock x 3 cycles. - (no wait time)
3 Set the VC25 bit in the VCR2 register to 1 (voltage detection 0 circuit enabled).
4 Wait for td(E (E-A).
Use bits VW0F0 to VW0F1 in the VW0C
Set the VW0C1 bit in the VW0C register to 1
5
register to select the digital filter sampling
clock. Set the VW0C1 bit to 0 (digital filter
(digital filter disabled), and bits 6 and 7 to 1.
enabled), and bits 6 and 7 to 1.
6 Set bit 2 in the VW0C register to 0. Set bit 2 to 0 once again after procedure 4.
7 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).
When using voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1
(digital filter disabled).
When voltage monitor 0 reset is generated, the CWR bit in the RSTFR register is automatically set to
0 (cold start-up). Refer to 6.4.4 “Voltage Monitor 0 Reset” for status after reset.
Figure 7.4 shows Voltage Monitor 0 Reset Operation Example.
VCC1
Vdet0
When the VW0C1 bit is 0
(digital filter enabled)
Internal reset signal
Digital filter sampling clock × 3 cycles
(1)
1
fOCO-S
× 32
When the VW0C1 bit is 1
(digital filter disabled)
Internal reset signal
1
fOCO-S
× 32
VW0C1: Bit in the VW0C register
The above diagram applies under the following conditions.
•The VC25 bit in the VCR2 register is 1 (voltage detection 0 circuit enabled).
•The VW0C0 bit in the VW0C register is 1 (voltage monitor 0 reset enabled).
The pins, CPU, and SFRs are initialized when the internal reset signal goes low.
The MCU executes the program at the address indicated by the reset vector when the internal reset signal changes from low to high.
Refer to 4. “SFRs” for the SFR status after reset.
Note:
1. Make sure that VCC1 does not drop to 2.7 V or below during sampling time.
Figure 7.4 Voltage Monitor 0 Reset Operation Example
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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